1. Field of the Invention
The invention relates to a semiconductor memory device and a method of fabricating the same, and more particularly to a semiconductor memory device including a charge pump circuit therein and a method of fabricating the same.
2. Description of the Related Art
A conventional non-volatile semiconductor memory device such as EEPROM and a flash memory has been provided with a step-up circuit when a higher voltage than a power source voltage is to be applied to a word line of a memory cell or a drain of MOS transistor. One of such step-up circuits is a charge pump circuit.
Hereinbelow is explained a semiconductor device having a charge pump circuit with reference to FIG. 1 which is a cross-sectional view of the semiconductor device and FIGS. 2A and 2B which are equivalent circuit diagram and time chart of clock signals to be provided to the semiconductor device in operation.
With reference to FIG. 1, there are formed device isolation films 32 at a surface of a silicon substrate 31 in selected areas to thereby define a device formation region therebetween. A plurality of gate insulating films 33 are formed on the silicon substrate 31 in selected areas in the device formation region, and there are formed a plurality of gate electrodes 34 on the gate insulating films 33. Diffusion layers 35a to 35n are formed at a surface of the silicon substrate 31 in self-aligned fashion with the gate electrodes 34 and the device isolation films 32 being used as a mask.
Thus, a plurality of MOS transistors are formed on a surface of the silicon substrate 31. These MOS transistors are electrically connected in series to each other. Each of the gate electrodes 34 of MOS transistors is electrically connected to the associated diffusion layer 35a to 35n. Step-up capacitors 37a to 37n are electrically connected in series to connection nodes 36a to 36n, respectively, through which the gate electrode 34 is electrically connected to each of the diffusion layers 35a to 35n. As illustrated in FIG. 1, two-phase clock signals "PHgr"1 and "PHgr"2 are applied to every other step-up capacitor 37a, 37c, . . . or 37b, 37d, . . .
The predetermined number of MOS transistors are electrically connected in series. An input voltage Vin is input through MOS transistor 39 to the connection node 36a electrically connected to the diffusion layer 35a of a first stage MOS transistor, and an output voltage Vout is obtained through the diffusion layer 35n of a final stage MOS transistor.
The operation of the above mentioned semiconductor memory device is explained hereinbelow. As illustrated in FIG. 2A, the semiconductor memory device includes the predetermined number of MOS transistors which are electrically connected in series and in which a gate electrode and a drain are shortcircuited through the connection node 36a to 36n. A parasitic capacitor 38 is connected to each of the connection nodes 36a to 36n. The parasitic capacitor 38 comprises a junction capacity between each of the diffusion layers 35a to 35n and the silicon substrate 31, and a part of a gate capacity of the associated MOS transistor. The two-phase clock signal "PHgr"1 or "PHgr"2 is applied to each of the connection nodes 36a to 36n through the associated step-up capacitor 37a to 37n. Thus, the input voltage Vin is applied to the connection node 36a electrically connected to the diffusion layer 35a of the first stage MOS transistor, and the output voltage Vout is led out through the diffusion layer 35n of the final stage MOS transistor.
As illustrated in FIG. 2B, negative phase clock signals "PHgr"1 and "PHgr"2 are alternately applied to the step-up capacitor 37a to 37n. For instance, in steady operation of the charge pump circuit, if a clock signal "PHgr"1 having a magnitude of Vcc is applied to the step-up capacitor 37a electrically connected to the first stage MOS transistor, a voltage at the connection node 36a of the first stage MOS transistor is increased by xcex94V1 defined by the equation (A).
xcex94V1=C1xc3x97Vcc/(C1+CS)xe2x80x83xe2x80x83(A)
In the equation (A), C1 indicates a capacity of the step-up capacitor 37a to 37n, CS indicates a capacity of the parasitic capacitor 38, Vcc indicates a voltage represented by the clock signals "PHgr"1 and "PHgr"2. At the same time when the clock signal "PHgr"1 is applied to the step-up capacitor 37a, a negative phase clock signal "PHgr"2 is applied to the step-up capacitor 37b of a next stage MOS transistor. Then, a voltage at the connection node 36b is lowered, and hence electric charges of the connection node 36a of the first stage MOS transistor is transferred to the next stage MOS transistor. In a manner as mentioned above, a voltage is increased through a plurality of MOS transistors.
In the above mentioned conventional semiconductor memory device, a charge pump circuit consumes much electric power for the reason explained below. In addition, a conventional semiconductor memory device having a charge pump circuit requires much area in which the device is to be fabricated.
In a conventional semiconductor memory device, the diffusion layers 35a to 35n have a great junction capacity, which in turn increases the capacity Cs of the parasitic capacitor 38, which further in turn lowers xcex94V1 as would be obvious in view of the equation (A). Accordingly, it is necessary for the step-up capacitors 37a to 37n to have a great capacity in order to a predetermined step-up in a voltage. As an alternative, it is necessary to increase the number of MOS transistor stages electrically connected in series. Thus, the above mentioned problems are posed.
The increased electric power consumption in a charge pump circuit would make it difficult to enable a semiconductor memory device to operate in a lower voltage and with lower electric power consumption.
An increased area required for forming a semiconductor memory device therein inevitably increases a chip area of a semiconductor memory device, which would make it difficult for a semiconductor memory device to have larger integration and greater capacity.
In view of the above mentioned problems in a conventional semiconductor memory device, it is an object of the present invention to provide a semiconductor memory circuit including a charge pump circuit with high step-up ability, and a method of fabricating the same.
In one aspect, there is provided a semiconductor memory device including a semiconductor substrate, a floating gate type transistor formed on the semiconductor substrate and acting as a memory cell of the semiconductor memory device, and a charge pump circuit formed on the semiconductor substrate, the transistor including (a) a first gate insulating film formed on the semiconductor substrate, (b) a floating gate electrode formed on the first gate insulating film, (c) a second gate insulating film formed on the floating gate electrode, and (d) a control gate electrode formed on the second gate insulating film, the charge pump circuit including (a) a plurality of diode devices formed on a third insulating layer formed on the semiconductor substrate, and electrically connected with each other in series, and (b) a plurality of capacitors each of which is electrically connected to a terminal of each of the diode devices.
For instance, the first gate insulating film may be a silicon dioxide film. The second gate insulating may be formed to have a multi-layered structure comprising a silicon dioxide film and a silicon nitride film. It is preferable that the floating gate electrode and the diode devices are made in a common film.
The floating gate electrode may be formed of a first silicon film formed on the first gate insulating film, and the diode devices may be constituted of pn junction diodes composed of p-type and n-type regions both formed of the first silicon film formed on the third insulating film. The first silicon film may be a thin amorphous silicon film.
It is preferable that each of the capacitors includes the p-type region as one of capacitor electrodes, a capacitor insulating film formed on the p-type region, and a second silicon film formed on the capacitor insulating film, as the other of capacitor electrodes. The second silicon film may be a polysilicon film, which preferably contains impurities therein. The second gate insulating film and the capacitor insulating film may be formed of a common insulating film.
The control gate electrode may be formed of the second silicon film. It is preferable that the n-type region has a higher impurity concentration than an impurity concentration of the p-type region. For instance, the third insulating film is a device isolation film formed on the semiconductor substrate in selected areas. The semiconductor memory device may further has a connection electrode for electrically connecting adjacent p-type and n-type regions to each other.
In another aspect, there is further provided a method of fabricating a semiconductor memory device, including the steps of (a) forming a device isolation film on a semiconductor substrate in selected areas thereof and also forming a first gate insulating film on a semiconductor substrate in a selected area thereof, (b) forming a first silicon film covering both the device isolation film and the first gate insulating film therewith, (c) converting predetermined regions of the first silicon film into p-type regions and the rest of regions into n-type regions, (d) forming a second gate insulating film covering the first silicon film therewith, (e) forming a second silicon film covering the second gate insulating film therewith, and (f) patterning the second silicon film and the second gate insulating film into a predetermined pattern.
The method may further include the step (g) of forming connection electrodes on the first silicon film for electrically connecting adjacent located p-type and n-type regions to each other.
In accordance with the above mentioned semiconductor memory device, a parasitic capacity of parasitic capacitors can be significantly reduced to thereby enhance a step-up efficiency. Thus, it is possible to reduce electric power consumption in a charge pump circuit and further reduce a total area required for a semiconductor memory device to be formed therein.
The reduction in electric power consumption of a charge pump circuit enables a semiconductor memory device to operate in a lower voltage and in lower electric power consumption. In addition, the reduction in an area required by a semiconductor memory device to be formed therein accompanies a reduction in a chip area of a semiconductor memory area, and facilitates larger integration and/or greater capacity in a semiconductor memory device.
In accordance with the above mentioned method, a semiconductor memory device having a charge pump circuit can be fabricated without so much increase in the number of steps. Thus, it is possible to prevent an increase in fabrication costs, improving cost performance.
The above and other objects and advantageous features of the present invention will be made apparent from the following description made with reference to the accompanying drawings, in which like reference characters designate the same or similar parts throughout the drawings.